1. Field of the Invention
The invention relates a semiconductor memory device having a function for measuring potential of data signal read out from a memory cell to a bit-line, a testing system and a testing method of the same.
2. Description of the Related Art
Semiconductor memory devices (semiconductor memories) such as dynamic random access memories (DRAM), static random access memories (SRAM), flash memories (Flash Memory), and ferroelectric memories (ferroelectric random access memory, or FeRAM) have been known. Specifications of the semiconductor memory devices such as circuit design, fabrication process, or reliability strongly depends on performance of the memory cell storing one bit of data, which is a unit of the memory. Therefore, when a semiconductor memory device is being developed, an approach is employed in which the performance required for a commercial product is improved through repeat of test fabrication with evaluating operation performance of the memory cell and feeding back the performance evaluation result to the device structure, fabrication process and circuit design.
In operation performance evaluation of above mentioned memory cells, read-out potential taken by reading out data pre-written to a memory cell to a bit-line, the data input/output line of the memory cell, which will be referred as “bit-line read-out potential” hereafter, is important information. For example, read-out potential after a certain time passed since data written to a memory cell, is a parameter representing a data hold performance of the memory cell. A read-out potential after repeat of writing to and reading from a memory cell is a parameter representing a repeat operation resistance.
Therefore, detailed evaluation of basic operation performance and reliability individual memory cells and yield of the memory cells in the whole set can be conducted by obtaining bit-line read-out potential with varying conditions such as power source potential or ambient temperature.
Bit-line read-out potential that is an internal signal of a semiconductor memory device is thus very important information for development of the semiconductor memory device. Techniques to measure precisely the internal signal of the semiconductor device are thus effective.
A ferroelectric memory will be described as a conventional semiconductor memory device, and a conventional technique to measure internal signal of a semiconductor memory device will be then described.
Circuitry and operation of ferooelectric memories are disclosed in detail, for example, in Japanese Patent Laid-Open No. 6-324558 and 10-233100. FIG. 1 shows arrangement of a memory cell array of a conventional ferroelectric memory and its periphery circuit, and FIG. 2 shows a timing chart of its operation. In FIG. 1, lines represented by a thin line are single line, and lines represented by a thick line are a set of multiple lines.
First, in FIG. 1, a memory cell array 110 is arranged by memory cells MCjk consisting of a transistor and a ferroelectric capacitor, so-called 1T/1C type, to a array with m rows and n columns, where “J” is a suffix representing a row number, having integer of 1 to m, and “k” is a suffix representing a column number, having integer of 1 to n. In following explanation, this representation using such suffix will be used in suitable manner. For example, a ward-line WLj represents any one of ward-line WL1 to WLm, and bit-line BLNk, BLTk represents any pair of BLN1, BLT1, -, BLNn, BLTn, in which they have a same number (for example, BLN1, BLT1).
A plurality of word-lines WL1-WLm and plate-lines PL1-PLm are wired such that the lines extend in row direction of the memory cell array 110, and a plurality of bit-lines BLTN1, BLT1, -, BLNn, BLTn are wired such that the lines extend in column direction perpendicular to the ward-lines and plate-lines. The word-lines WLj and plate-lines PLj are lines for selecting a memory cell belonging to the row of row-number j and are driven selectively by a row decoder 120 described below. The gate terminal of the transistor in memory cell MCjk is connected to word-line WLj and the drain terminal is connected one of a pair of bit-line, BLNk or BLTk described below. One electrode of the ferroelectric capacitor of the memory cell is the source terminal of the transistor of the memory cell, and the other electrode is connected to plate-line PLj.
Bit-lines BLNk, BLTk belonging to row-number k form a pair, and memory cells connected to word-lines adjacent to each other are connected to the pair of bit-lines BLNk, BLTk, respectively, and they are adapted such that memory cells connected respectively bit-lines forming a pair can not be selected simultaneously. Sense amps SA1 to San for amplifying data signal, which is read from memory cells for each pair of bit-line BLNk, BLTk, is connected to bit-lines BLN1, BLT1, -, BLTn, BLTn. The sense amps SA1-SAn are controlled with sense amp activation signal SAE generated at a sense amp control circuit 181 described below.
Bit-line precharge circuits PBL1-PBLn for initializing bit-line potential in read-out are connected to bit-lines BLN1, BLT1 to BLNn, BLTn, respectively for each pair of bit-line BLNk, BLTk. These bit-line precharge circuits PBL1-PBLn are controlled with bit-line precharge signal PBL generated by a bit-line precharge control circuit 182 described below so as to initialize each bit-line potential to the ground potential.
Dummy memory cells DCN1, DCT1, -, DCNn, DCTn are connected to bit-line BLN1, BLT1, -, BLN1, BLTn respectively. The dummy memory cells are used for generating reference potential required in read-out step, and have an arrangement equivalent to above mentioned 1T/1C memory cell MCjk. Dummy memory cells DCN1-DCNn correspond to memory cells connected to bit-line BLN1-BLNn, and are connected to a dummy word-line DWLN. Dummy memory cells DCT1 to DCTn correspond to memory cells connected to bit-line BLT1-BLTn, and are connected to a dummy word-line DWLT.
Column selection transfer gates YST1-YSTn are connected to bit-lines BLN1, BLT1-BLNn, BLTn, respectively for each pair of bit-line BLNk, BLTk, and bit-line BLN1, BLT1, -, BLNn, BLTn are selectively connected to a DB line (complimentary signal line) though the column selection transfer gates YST1-YSTn. Column selection line YSW1-YSWn from a column decoder 130 described later are connected to the column selection transfer gates YST1-YSTn.
An address predecoder 160 predecodes address signal Ai that is input from outside of the device, to generate row address predecode signal XPa and column address predecode signal YPb. The row decoder 120 drives selectively the word-lines WL1-WLm based on the row address predecode signal XPa generated by the address predecoder 160, so as to select a row of memory cells. In this embodiment 1, the row decoder 120 includes a function for selecting the plate-line PL1-PLm. The column decoder 130 drives selectively the column selection lines YSW1-YSWn based on column address predecode signal YPb generated by the address predecoder 160, so as to select a column of memory cells (a group of memory cell connected to a pair of bit-line BLNk, BLTk). In addition to the above described components, an input/output buffer circuit for data (not shown specifically) is also connected the data line DB.
Next, with reference to FIG. 2, operation of the ferroelectric memory shown in FIG. 1 will be described in the case where data reading and writing are performed with a memory cell MC22 being selected.
First, the ferroelectric memory is in waiting states. In the waiting states, all of the word-lines WL1-WLm, plate-lines PL1-PLm, dummy word-line DWLN, DWLT, and column selection lines YSW1-YSWn are driven to low-level, and the sense amp activation signal SAE is set to low-level. All of memory cells MC11-MCmn, dummy memory cells DCN1, DCT1, -, DCNn, DCTn, sense amps SA1-SAn, and column selection transfer gates YST1-YSTn are thus made in inactivated states. Bit-line precharge signal PBL is set to high-level, and bit-line precharge circuit PBL1-PBLn are made in activated states. Thus, potentials of bit-line BLN1, BLT1, -, BLNn, BLTn are driven to the ground potential by bit-line precharge circuits PBL1-PBLn, and all the bit-lines are precharged to the ground potential.
When writing operation or reading operation is performed from the above waiting state, first, bit-line precharge signal PBL is set to low-level. The bit-line precharge circuits PBL1-PBLn are thus inactivated, and all the bit-line become in floating states. At this point, since the bit-line BLN1, BLT1, BLNn, BLTn have been precharged to the ground states before, potential of each bit-line maintains low-level (the ground potential) while influence of leak or the like is negligible.
Memory cell 22 is then selected. Specifically, based on address signal Ai assigned from the outside, word-line W2 is driven to high-level, and plate-line PL2 is driven to high-level. The high-level potential of the word-line WL2 is typically an elevated potential about Vtn higher than the power source potential because of necessity for compensating the amount of threshold potential of the transistors forming the memory cells. The high-level of the plate-line PL2 is typically the source potential.
The word-line WL2 and plate-line PL2 is driven to high-level to make all memory cells MC21, MC22, . . . , MC2n in selection states. In other words, the plate-line PL2 is driven to high-level to generate a potential difference between the plate-line PL2 and the bit-lines BLT1-BLTn. A potential difference thus occurs between electrodes of ferroelectric capacitors in the memory cells belonging to the row number j of “2”, and electric charge corresponding to the potential difference is output from the ferroelectric capacitors to the bit-line BLT1-BLTn. As a result, bit-line read-out potentials, which are potentials of data signals, occur on the bit-lines BLT1-BLTn. The bit-line read-out potential has typically an analog value between the source potential and the ground potential.
On the other hand, reference potentials for determining if the bit-line read-out potentials occurring on the bit-lines BLT1-BLTn correspond to data “0” or data “1” are generated on bit-line BLN1-BLNn pairing with bit-line BLT1-BLTn. In this case, the reference potentials occur on the bit-lines BLN1-BLNn by driving the dummy word-line DWLN to high-level to select dummy cells DCN1-DCNn.
In contrast, when determination for data corresponding to bit-line read-out potentials on the bit-lines BLN1-BLNn is made, the dummy word-line DWLT is driven to high-level to select dummy memory cells DCT1-DCT so as to generate reference potentials on the bit-lines BLT1-BLTn. Methods for generating such a reference potential are disclosed in detail, for example, in Japanese Patent Laid-Open No. 10-233100 and Japanese Patent Laid-Open No. 9-97496.
Read-out potentials are thus output to the bit-lines BLT1-BLTn from memory cells MC21-MC2n belonging to the row number j of “2”, and reference potentials are output to the bit-line BLN1-BLNn from dummy memory cells DCN1-DCNn. After that, the sense amps SA1-SAn are activated by making the sense amp activation signal SAE high-level, and the potential difference between bit-line BLNk and bit-line BLTk paring with each other is differentially amplified.
At this point, in the case of data read-out operation, the column selection line YSW2 is driven to high-level to activate the column selection transfer gate YST2. Electrical connection between a pair of bit-lines BLN2, BLT2 and the data-line DB is thus made to transfer the differentially amplified data signal on the pair of bit-lines BLN2, BLT2 to a data output buffer circuit (not shown). This data output buffer circuit outputs data to outside. In the case of data write operation, data is input from outside by a data input buffer circuit (not shown). Potential corresponding to data is output through the data-line DB to write the data to the pair of bit-lines BLN2, BLT2 to write the data to the memory cell MC22.
The data read-out operation described above is so-called destructive read-out operation in which stored data in the memory cell is destroyed during data read-out step. When stored data is to be maintained after read-out, the data is rewritten to the memory cell. In the ferroelectric memory, data writing to the memory cell is implemented by following operations:    (1) If rewriting data “0”, starting from status where the bit-line is driven to low-level and the plate-line is driven to high-level, the plate-line is driven to low-level and the voltage applied to the ferroelectric capacitor is made to zero.    (2) If rewriting data “1”, starting from status where the bit-line is driven to high-level and the plate-line is driven to low-level, the bit-line is driven to low-level and the voltage applied to the ferroelectric capacitor is made to zero.
With reference to the timing chart in FIG. 2, data writing operation will be further described in detail. For example, in the case of a memory cell coupled with the bit-line BLT2 that is low-level after data amplification by the sense amp SA2, starting from status where the plate-line PL2 has been driven to high-level and the bit-line has been driven to low-level beforehand, voltage applied to the ferroelectric capacitor become zero when the plate-line PL2 is driven to low-level. Therefore, after the column selection line YSW2 is driven to low-level, the data writing is completed at the time when the plate-line PL2 is driven to low-level.
In the case of a memory cell coupled with the bit-line BLN2 that is driven to high-level after data amplification by the sense amp SA2, when the plate-line PL2 is driven to low-level, the bit-line BLN2 is driven to high-level, and next, when the bit-line BLN2 is driven to low-level, voltage applied to the ferroelectric capacitor in the memory cell become zero. Therefore, the data rewriting is completed at the time when the sense amp activation signal SAE is made low-level and the bit-line precharge signal PBL is made high-level and the bit-line potential is made to the ground potential (low-level).
After completion of the data rewriting, the word-line WL2 is driven to low-level to make back the memory cell no-selection status. One cycle of read-out operation or writing operation for the ferroelectric memory is thus completed.
The operation of the ferroelectric memory described so far is operation for storing one bit of data for a memory cell of 1T/1C type memory cells, and it is so-called “1T/1C type operation method”. In this operation method, reference potential is needed in read-out operation. In contrast, there is a operation method wherein one bit of data is stored with two 1T/1C type memory cells, which is so-called “2T/2C type operation method”.
In the 2T/2C type operation method, one memory cell of 1T/1C type memory cells connected to bit-line BLNk and one memory cell of 1T/1C type memory cells connected to bit-line BLTk are formed in a pair, with the pair of memory cells being 1-bit memory unit. This will be explained by using FIG. 1. Pairs of memory cells as a 1-bit memory unit is set up, such as, for example, memory cell MC11 and memory cell MC21 for a pair of bit-line BLN1, BLT1, memory cell MC12 and memory cell MC22 for a pair of bit-line BLN2, BLT2, and so on. Data that have opposite polarization to each other (complementary data) are held in the pair of memory cells.
For example, the status where high-level data signal occurs on the bit-line BLTN1 and low-level data signal occurs in the bit-line BLT1, is adapted to be data “0”, and the opposite status is adapted to be data “1”. One bit of data is thus stored by the two 1T/1C type memory cells. In this operation method, differential amplification operation with the sense amp can be performed without requiring reference potential used in the case of the 1T/1C type operation method above-mentioned, since complementary data signals depending on the data content are output onto bit-lines BLNk, BLTk from the memory cell itself.
As explained so far, bit line read-out potential for ferroelectric memory is analog value, either in the 1T/1C type operation or in the 2T/2C typed operation. Therefore, in the case of measuring bit-line read-out potential, a method wherein analog potential value is measurable, must be used. This requirement is same for other semiconductor memory devices, not limited to ferroelectric memory.
Next, conventional techniques for measuring internal signals in a semiconductor memory device, including bit-line read-out potential will be described. As such conventional techniques, followings are known:    (1) Japanese Patent Laid-Open No. 8-241589 discloses a method for contacting a probe to a node with signal for measured object to directly measure the potential of the signal.    (2) Japanese Patent Laid-Open No. 5-129553 discloses a method for using an electron beam (EB) tester to measure.    (3) Japanese Patent Laid-Open No. 10-233100 discloses a semiconductor memory device comprising a bit-line potential detection means. A technique disclosed in the application is such that bit-line read-out potential is measured by seeing if the bit-line read-out potential to be measured exceeds the sensitivity of the sense amp, which is the potential disabling normal amplification operation with the sense amp.
However, according to the conventional techniques above described for measuring internal signals have following disadvantages.    (1) In the method using a probe disclosed in the Japanese Patent Laid-Open No. 8-24158, the operation needs much time since the probe has to be moved onto bit-lines in a memory cells formed on surface of a semiconductor chip, by controlling a manipulator or the like. Additionally, when bit-line read-out signals occurring on a plurality of bit-lines are measured, the operation needs much longer time since it is needed to move the probe onto every bit-lines. In order to eliminate these disadvantages, there may be a method wherein probes are moved to all the bit-lines simultaneously, however a dedicated measurement jig should be prepared since it is very difficult to move the plurality of probes onto a plurality of bit-lines fine-processed.    (2) In the methods using EB tester disclosed Japanese Patent Laid-Open No. 5-129553, there is a problem of increased cost because of high price of the EB tester equipment. Furthermore, there is another problem that it is difficult to measure absolute value of measured object potential since EB tester only obtains relative value due to the tester's characteristic.    (3) In the technique disclosed in Japanese Patent Laid-Open No. 10-233100, there is a problem that the technique is not suitable to measurement of analog bit-line read-out potential since it only determines if the bit-line read-out potential of a measured object exceeds the sense amp sensitivity.
According to the conventional techniques above mentioned, there is a difficulty in measuring analog bit-line read-out potential.
There is also a particular problem on measuring bit-line read-out potential.
The problem is that, once large capacitive load or current load is connected to the bit-line itself, due to the load's influence, the potential of a measured object varies, resulting in different potential from the true bit-line read-out potential. Therefore, it is needed to limit the capacitive load added to a bit-line, which is came from a measurement part to measure potential of bit-line, within, for example, less than 10 percent of the parasitic capacitance, which the bit-line has in itself.
Another problem is that, in the case of a semiconductor memory device such as dynamic random access memory or ferroelectric, where data signal is read out from memory cell to a bit-line in floating state, it is needed to limit influence of leak current when bit-line read-out potential is measured.
FIG. 3 shows a structure of a memory cell that a ferroelectric memory has, and an example of leak current that affects bit-line read-out potential.
FIG. 3(a) shows a circuitry of a memory cell, and FIG. 3(b) shows schematically a cross section of a memory cell. In FIGS. 3(a) and (b), transistor Tr is used to make electrical connection between storage node M and bit-line BL depending on potential of word-line WL, and source DS is connected to the storage node M and drain DD is connected to the bit-line BL, and gate GT is connected to ward-line WL. The ferroelectric capacitor Cf is used to hold data, and comprises upper electrode TU and lower electrode TL and the upper electrode TU is connected to the storage node M (the source DS of the transistor Tr), and the lower electrode TL is connected to plate-line PL.
As shown in FIG. 3(b), leak current that affects bit-line read-out potential includes various leak currents such as inter-layer leak current i1 through inter-layer insulator film ML to adjacent line, gate oxide film leak current i2 to gate GT of the memory cell, channel leak current i3 in subthreshold region, junction leak current i4 between a diffusion layer (drain DD) and substrate SUB, and leak current i5 to diffusion layer of adjacent memory cell.
Because of the existence of such various leak currents, bit-line read-out potential in floating state varies with time increasing, and when some time is needed to measure bit-line read-out potential, influence of above mentioned leak currents is not negligible and precise measurement of bit-line read-out potential cannot be conducted. It is thought that time acceptable for one measurement step for bit-line read-out potential is generally less than 1 millisecond while it depends on magnitude of the leak current (, which depends on memory cell structure and fabrication process conditions of the semiconductor memory device).
As described above, in order to precisely measure bit-line read-out potential, it is needed to minimize the capacitive load added the bit-line, which attributes to a measurement part, and to limit the influence of the leak currents.